1. Field
This patent specification relates to a voltage reference generation circuit comprising MOS or CMOS transistors, and an apparatus incorporating such generation circuit exemplified by a power source, which is suitably in use for relatively small electronic devices such as hand-held cellular phones, for example.
2. Discussion of the Background
As the use of hand-held apparatuses becomes more widespread, numerous efforts have been made to provide reliable power supplies for these apparatuses with appropriate voltage reference generation circuits.
It has been disclosed previously in Japanese Laid-Open Patent Application No. 56-108258 to provide a voltage reference generation circuit including a depletion-mode MOS transistor with its gate and drain interconnected to be utilized as a constant current source. In that disclosure, the gate and the drain of the depletion-mode MOS transistor Q1 are interconnected as shown in FIG. 1, in which a constant current from the MOS transistor is supplied to succeeding transistor circuits.
Namely, each having a gate and a drain interconnected, enhancement-mode MOS transistors Q12 and Q13 are further connected in series to be operated by the constant current supplied by the MOS transistor Q1. Reference voltages are then obtained from the voltages generated by these transistors Q12 and Q13.
Incidentally, the MOS transistors Q1, Q12 and Q13 are all of N-channel type. In addition, the portion of the transistors Q12 and Q13 illustrated in FIG. 1 may be displaced by either a single transistor (FIG. 6) or more than two transistors. Also shown in FIG. 1 are a couple of junctions and values of the potential voltages, V02 and V03, at respective junctions.
In the case of the above noted single transistor illustrated in FIG. 6, a reference voltage is obtained as the difference between the threshold voltage Vtxe2x80x94d of depletion-mode MOS transistor Q21 and the voltage at Vtxe2x80x94e of enhancement-mode MOS transistor Q22.
There is an embodiment in Application 4-65546 regarding to methods for forming MOS transistors Q21 and Q22 (FIG. 6) having different values of threshold voltage, in which the difference is affected by varying the impurity concentration in substrates and/or channel regions of respective transistors, that is achieved by, for example, changing the number of ions in ion implantation process steps.
Although no description is found in that disclosure for utilizing the above noted two transistors Q12 and Q13 (FIG. 1), it is noted that threshold difference in depletion-mode MOS transistor Q1, and enhancement-mode MOS transistors Q12 and Q13, such as described herein below, may similarly be effected by varying impurity concentrations in substrates and/or channel regions.
In addition to the voltage reference generation circuit of FIG. 1, a further voltage reference generation circuit may alternatively be formed as illustrated in FIG. 2, which includes a MOS transistor having its gate and drain interconnected so as to serve as a constant current source.
Referring to FIG. 2, there included in the circuit are the same depletion-mode MOS transistor Q1 as that of FIG. 1, an enhancement-mode MOS transistor Q2 having a low threshold voltage Vtl and another enhancement-mode MOS transistor Q3 having a higher threshold voltage Vth. In this construction of the voltage reference generation circuit, a reference voltage is obtained as the difference between these threshold voltages Vth and Vtl of the enhancement-mode MOS transistors Q3 and Q2, respectively.
FIG. 3 includes graphical plots of (Ids)1/2 as a function of Vgs for the MOS transistors Q1, Q2 and Q3 at a saturated drain voltage, where Ids is the drain current and Vgs is the voltage between gate and source. The conductance factor K is assumed the same for respective transistors.
Since the gate and source of MOS transistor Q1 are interconnected and the value of Vgs is therefore zero and fixed, the constant current supplied by Q1 is found to be Iconstant as shown in FIG. 3. Accordingly, the values of Vgs for satisfying the relation Ids=Iconstant are found to be V02 and V03 for the transistors Q2 and Q3, respectively. The reference voltage VREF is subsequently obtained as the difference between these two values;                               V          REF                =                ⁢                                            V              0                        ⁢            3                    -                                    V              0                        ⁢            2                                                  =                ⁢                                            V              t                        ⁢            h                    -                                    V              t                        ⁢                          l              .                                          
The VREF value is therefore obtained as the difference between two thresholds Vth and Vtl.
Several advantages may be noted in regard to the generation of the reference voltage VREF with this generation circuit, which follows.
(1) Since the VREF value is obtained as the difference between threshold values, as mentioned above, the dispersion of VREFis relatively unaffected by the fluctuation of constant current, which is caused by the dispersion of the threshold voltage of the depletion-mode MOS transistor. As a result, the dispersion of VREF is relatively small.
(2) Because of the approximately same temperature characteristics of the MOS transistors Q2 and Q3, the dependency of VREF value on temperature is relatively small,
and (3) since the present circuit may be formed consisting of as few as three MOS transistors, the present circuit can be fabricated with more ease in a smaller area than the bandgap reference circuit.
As is known, this bandgap reference circuit is designed with a PN junction so as to output a relatively small voltage reference VREF having a considerably reduced temperature coefficient, utilizing both its base-emitter voltage Vbe and thermal voltage Vt(=kT/q, where k is Boltzman""s constant, T the absolute temperature and q the electron""s charge). It may also be added in this context that these voltages Vbe and Vt have the opposite polarity of temperature dependence to thereby generate compensating resultant voltages, which are appropriately utilized in this circuit.
For the aforementioned single transistor case illustrated in FIG. 6, the relation between threshold voltages and voltage reference from the generation circuit may be considered in a similar manner, which follows.
FIG. 7 includes graphical plots of (Ids)1/2 as a function of Vgs for the aforementioned MOS transistors Q21 and Q22 at a saturated drain voltage, where Ids is the drain current and Vgs is the voltage between gate and source. The conductance factor K is assumed same for respective transistors.
Since the gate and source of MOS transistor Q21 are interconnected and Vgs is therefore zero and fixed, the constant current supplied by Q21 is found to be Iconstant as shown in FIG. 7. Accordingly, the Vgs value of the transistor Q22 for satisfying the relation Ids=Iconstant is found as to be VREF,
VREF=Vtxe2x80x94exe2x88x92Vtxe2x80x94d. 
As a result, the VREF value is given as the difference between two threshold voltages Vt_e and Vt_d.
Several advantages can also be noted in regard to the reference voltage generation with the present circuit, which follows. (1) Because of the approximately same temperature characteristics of the MOS transistors Q21 and Q22, the dependency of VREF value on temperature is relatively small, and (2) since the present circuit may be formed consisting of as few as two MOS transistors, the present circuit can be fabricated with more ease in a smaller area than the aforementioned bandgap reference circuit.
In addition, the present circuit can offer another advantage. Namely, after a slight modification thereof, exemplified by a wire connection change of the gate of MOS transistor Q21, another voltage reference generation circuit can be formed, which is capable of supplying relatively small reference voltages (Japanese Laid-Open Patent Application No. 8-335122). The thus formed generation circuit is illustrated in FIG. 8, in which the gate of MOS transistor Q21 is grounded, indicating the difference from the FIG. 6 circuit after the modification.
The above noted capability of this circuit for generating small reference voltages is explained as follows.
There assumed for the depletion-mode MOS transistor Q21 are a threshold voltage Vtxe2x80x94d, drain current Idsxe2x80x94d and source-gate voltage Vgsxe2x80x94d. Also assumed for the enhancement-mode MOS transistor Q22 are a threshold voltage Vtxe2x80x94e, drain current Idsxe2x80x94e and source-gate voltage Vgsxe2x80x94e. In addition, the conductance factor K is assumed the same for the both transistors.
The drain currents Idsxe2x80x94d and Idsxe2x80x94e for the MOS transistors Q21 and Q22, respectively, are given as follows.
Idsxe2x80x94d=K(Vgsxe2x80x94dxe2x88x92Vtxe2x80x94d)2, 
and
Idsxe2x80x94e=K(Vgsxe2x80x94exe2x88x92Vtxe2x80x94e)2. 
Accordingly, after the relations
Idsxe2x80x94d=Idsxe2x80x94e 
and
Vgsxe2x80x94d=xe2x88x92Vgsxe2x80x94e, 
a constant gate-source voltage Vgsxe2x80x94e is obtained as
K(xe2x88x92Vgsxe2x80x94exe2x88x92Vtxe2x80x94d)2=K(Vgsxe2x80x94exe2x88x92Vtxe2x80x94e)2 
Vgsxe2x80x94e=(Vtxe2x80x94exe2x88x92Vtxe2x80x94d)/2. 
The VREF value is therefore given as VREF=(Vtxe2x80x94exe2x88x92Vtxe2x80x94d)/2, which is appropriately utilized for generating relatively low reference voltages.
In order to achieve higher accuracy in reference voltages VREF, however, the aforementioned generation circuits have several drawbacks, which follows.
For the two transistor construction shown in FIG. 2:
(1) Since threshold voltages Vth of respective transistors are determined by ion implantation process carried out individually for each transistor, dispersion in Vth is effected independently of each other and this may result in large dispersion of the difference in Vth values and hence in VREF. FIG. 4 includes graphical plots of (Ids)1/2 versus Vgs for the transistors Q2 and Q3 affected by the dispersion, in which Vth is shifted to a lower value for the former transistor, while to a higher value for the latter, for example. Two dashed straight lines also included in FIG. 4 indicate the plots without the dispersion.
(2) Since the channel profile is different for respective transistors, the temperature dependence of threshold voltage and mobility is not strictly the same for each other. The improvement of temperature characteristics is therefore rather limited. FIG. 5 includes graphical plots of (Ids)1/2 versus Vgs for the transistors Q2 and Q3 at higher temperatures, in which Vth is shifted differently for respective transistors. This is resulted from the change in slope due to the aforementioned difference in channel profile, among others. Two dashed straight lines also included in FIG. 5 show the plots prior to the increase in the temperature.
For the single transistor structure of FIGS. 6 and 8:
(1) In a manner similar to the two transistor structure mentioned earlier, since threshold voltages Vtxe2x80x94d and Vtxe2x80x94e of the transistors Q21 and Q22, respectively, are determined by ion implantation process carried out individually for each transistor, the dispersion in Vth is effected independently of each other and this may result in a large dispersion of the difference in Vth values and hence in VREF. FIG. 9 includes graphical plots of (Ids)1/2 versus Vgs for the transistors Q21 and Q22 affected by the dispersion, in which Vtxe2x80x94e is shifted higher for the transistor Q22. A dashed straight line also included in FIG. 9 shows the plot without the dispersion.
(2) Since the conductivity type of implanted ions is different for respective transistors Q21 and Q22, the temperature dependence of threshold voltage and mobility is not strictly the same for each other. The improvement of temperature characteristics is therefore rather limited. FIG. 10 includes graphical plots of (Ids)1/2 versus Vgs for the transistors Q21 and Q22 at higher temperatures, in which Vtxe2x80x94e for the transistor Q22 is shifted, that is caused by its slope change due to the aforementioned difference in conductivity type, among others.
(3) In addition, since there exists a limitation in the range of Vtxe2x80x94d value for the depletion-mode MOS transistor in the aforementioned modified voltage reference generation circuit of FIG. 8 (the Application No. 8-335122), a relatively large margin in device fabrication has to be allocated for the temperature change and the fluctuation of process parameters. In the voltage reference generation circuit shown in FIG. 6 (22), since the limitation in the range of Vtxe2x80x94d value is expressed by the relation |Vtxe2x80x94| greater than VREF greater than Vtxe2x80x94e, the Vtxe2x80x94d value of the depletion-mode MOS transistor has to be adjusted smaller than that of the FIG. 2 circuit so as to satisfy the above relationship.
Accordingly, it is an object of the present disclosure to provide a voltage reference generation circuit and an apparatus incorporating such generation circuit having most, if not all, of the advantages and features of similar employed circuits and apparatuses, while eliminating many of the aforementioned disadvantages.
It is another object of the present disclosure to provide a voltage reference generation circuit capable of generating reference voltages that are stable to the change in the temperature and unaffected by the fluctuation of process parameters during fabrication steps. The reference voltages may be small enough depending on the way of use.
The following brief description is a synopsis of only selected features and attributes of the present disclosure. A more complete description thereof is found below in the section entitled xe2x80x9cDescription of the Preferred Embodimentsxe2x80x9d
The voltage reference generation circuit of the present invention includes a depletion-mode MOS transistor configured to serve as a constant current source by having its gate and drain interconnected. At least two enhancement-mode MOS transistors are connected in series to the depletion-mode MOS transistor and configured to operate at a saturated drain voltage by the current supplied by the depletion-mode MOS transistor. The junction of the enhancement-mode MOS transistors and another junction of the depletion-mode MOS transistor and enhancement-mode MOS transistors are configured to serve as output terminals. The enhancement-mode MOS transistors have the same channel dopant profile and different threshold voltages.
The at least two enhancement-mode MOS transistors include two transistors having their gates interconnected, and the junction of these two MOS transistors serves as one of the output terminals. The gate and drain of each of the enhancement-mode MOS transistors are interconnected.
In addition, each of the enhancement-mode MOS transistors is provided with a floating gate to have a different threshold voltage depending on the coupling coefficient between the floating gate and the control gate, the amount of charge input to the floating gate, the kind of dielectric material included in the gate, and the thickness of a gate oxide layer included also in the gate.
According to another aspect, a voltage reference generation circuit disclosed herein includes a voltage reference generating stage and a voltage reference output stage, in which at least two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, a gate of one of the enhancement-mode MOS transistors is connected to an output terminal of the voltage reference generating stage, a gate and a drain of the enhancement-mode MOS transistors other than the one are interconnected, and a junction formed between the enhancement-mode MOS transistors other than the one serves as an output terminal for a voltage reference.
In addition, each of the enhancement-mode MOS transistors may consist of a group of paired transistors formed in the common-centroid structure. Further, each of the enhancement-mode MOS transistors has the same beta value, and is formed so as to satisfy the following relation
TOX/(LW)1/2xe2x89xa61.5xc3x9710xe2x88x923, 
where L is the channel length, W the channel width and TOX the gate thickness.
According to still another aspect, a power source is provided, including a voltage reference generation circuit and a detection circuit configured to compare a supplied voltage to the reference voltage generated by the voltage reference generation circuit, in which the voltage reference generation circuit is selected from those generation circuit embodied herein above.
The present disclosure and features and advantages thereof will be more readily apparent from the following detailed description and appended claims when taken with drawings.